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Current Trends in Science and Technology

an Open Access Publication ISSN: 0976-9730 | 0976-9498

Engineering and Technology

Implementation and Evaluation of Redundant and Irredundant Bus Encoding Techniques for Low Power VLSI

Shankaranarayana Bhat M, Shubham Agiwal,Dylan Bosco Fernandes, K.M.Balakrishna
1Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal University, Manipal, Karnataka, India. 2Student, Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal University, Manipal, Karnataka, India. 3Department of Physics,Mangalore University, Mangalagangothri, Konaje, Mangalore, Karnataka, India.
Online First: October 13, 2017
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Abstract

Power dissipation on busses has become a concern in VLSI circuits and systems with continuous scaling down of the feature size and increasing data rates. The primary focus of the VLSI industry being the reduction of power in modern electronic systems, bus encoding techniques gain importance. These techniques involve reduction of the switching activity on the bus, which helps reduce the power dissipation occurring during the data transfer. In this paper, an analysis of various bus encoding techniques for their switching activity reduction, power saving, area, and delay is carried out. Power dissipation of the bus encoder and decoder employing different techniques has been evaluated.The physical design of the encoders and decoders was donein 45nm technologyusing Cadencetool and the power, area, and delay were evaluated.

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Oct 13, 2017
Published
Oct 13, 2017
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