Power dissipation on busses has become a concern in VLSI circuits and systems with continuous scaling down of the feature size and increasing data rates. The primary focus of the VLSI industry being the reduction of power in modern electronic systems, bus encoding techniques gain importance. These techniques involve reduction of the switching activity on the bus, which helps reduce the power dissipation occurring during the data transfer. In this paper, an analysis of various bus encoding techniques for their switching activity reduction, power saving, area, and delay is carried out. Power dissipation of the bus encoder and decoder employing different techniques has been evaluated.The physical design of the encoders and decoders was donein 45nm technologyusing Cadencetool and the power, area, and delay were evaluated.
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