This paper presents design and physical realization and Synthesis of Walsh Pattern Generator on CPLD. The overall architecture for Walsh pattern generation is programmed in a Xilinx Design Tools 8.2i and to be synthesized for the programmable devices such as CPLD; thus, to develop a SOC. A description of the hardware's structure and behavior is written in VHDL language and that source code is then compiled and downloaded prior to execution. Physical realization of the design was confirmed by obtaining RTL structure and Synthesis report. The simulation results obtained have been compared with the calculated results by hardware implementation.
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