MC

Current Trends in Science and Technology

an Open Access Publication ISSN: 0976-9730 | 0976-9498

Engineering and Technology

Automated Design of Low-Noise High-Gain CMOS Two-stage Operational Amplifier via Thermal Noise Optimization Methodology

Ch. Lison Singh , A. J. Gogoi Ch. Anandini , K. L. Baishnab
National Institute of Technology, Silchar Assam,
Online First: September 03, 2017
| Google Scholar

Abstract

Design of complex analog circuit accurately requires the design process to be automated. The automated
design process not only gives accurate results but also minimizes the cost and robustness of the complex
analog system. Proper analysis of noise presence in the circuit with respect to circuit area can help in
realization of High-gain analog circuit with least minimum possible circuit area. This paper presents an
automated Human Behavior-Based Particle Swarm Optimization (HPSO)-design methodology,
incorporating noise as design specification, for designing a Low-noise High-gain Two-stage Op amp.
Swarm Intelligence (SI) based PSO has an ability to approximate optimal solution within an acceptable time,
here, HPSO is used to explore the search space and handle constraints of the design problem to efficiently
design the circuit without incurring much resources. The presented design methodology gives an in-sight
into realization of High-gain analog circuit without increasing circuit area via incorporating thermal noise in
the design process and adoption of automated design process eliminated the tediousness and time consuming
process in determining global optimal solution of the circuit.The MATLAB simulated results of HPSO-
based design procedure is linked with CADENCE simulation tool with UMC 0.18 μm technology parameter
model to evaluate the performance of the circuit design through global optimal solutions. Further, the
efficiency of the presented design procedure is checked by comparing with previous automated design
methodology based on SI.

Keyword : HPSO, Two-stage Op-amp, Thermal noise optimization, Circuit area optimization.

  Submitted
Sep 3, 2017
Published
Sep 3, 2017
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